The present invention relates to a computer system. More particularly, it relates to an improved random access memory assembly for a computer.
Heretofore, there have been provided computer systems having random access memory assemblies or cards. These systems have included means for detecting errors in the data stored in the random access memory unit (RAM). Such systems have usually provided means for detecting a single error or a double error and with a capability of correcting a single error in the transmitted data derived from the RAM. As noted, the system is capable of correcting single errors in the forward transmission of data. If a double error occurs, an alarm is effected and the system either shuts down or bypasses the erroneous data. In either event, the double error constitutes a fatal error so far as the affected transaction is concerned. If a single error occurs on one cycle of reading from the RAM, the forward transmission is corrected but the error remains in the RAM. If, on a subsequent addressing of the RAM, a second error appears, that second error becomes cumulative with the first error and, therefore, becomes a fatal double error.